1. Field of the Invention
The present invention relates to a multiplier circuit, an adder circuit constituting part of the multiplier circuit, a partial product bit compression method for the multiplier circuit, and a large-scale semiconductor integrated circuit using the multiplier circuit, and more particularly, to a multiplier circuit which is reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.
2. Description of the Related Art
In recent years, with rapid advances in manufacturing and design technologies of large-scale semiconductor integrated circuits, exemplified by microprocessors and digital signal processors, a demand for high-speed, large-scale arithmetic circuits has been increasing. In particular, for multiplier circuits that require long calculation times and a larger number of circuits, high-speed circuits with reduced number of elements are needed.
The prior arts and their associated problems will be described in detail later with reference to the accompanying drawings.